Title: ASIC Design Verification Engineer 3 Duration: 6 Months Contract Location: Markham, ON (Onsite/Hybrid) Pay Range: $70 – $75/hour on T4

THE ROLE As a member of verification team, you will work with leading industry tools and design & verification concepts to achieve full functional, performance & power verification closure on a variety of digital design blocks which are a part of the Graphics Core IP (GFXIP). You will work closely with architects, designers and other design verification engineers to author testplan for pre-silicon verification, planning & development of testbenches to exercise the design, write detailed testplans to cover new blocks and features, drive the development of test-cases and coverpoints or assertions to achieve verification closure.

JOB DESCRIPTION Verification Ownership Be responsible for functional, power and performance verification of a block, including verification planning, execution and DV closure; Work closely with the architect, RTL designers and other verification engineers to achieve verification closure within project schedules; Verification Planning & Coverage Develop and execute test and coverage plans to ensure the functional, performance and power completeness; Testbench & Verification Development Create, reuse and debug testbenches, verification components and tests for verification of the design; Methodology & Infrastructure Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects. EXPERIENCE AND EDUCATION Experience Minimum 5+ years of verification experience on large ASIC development projects; Experience working with UVM, OVM or equivalent; Experience with constrained random verification, functional coverage and assertions; Experience with formal verification is an added advantage; Experience working with industry standards tools such Synopsys VCS, VC Formal, DVE, Verdi, GDB or equivalent; Technical Skills Solid understanding of Computer Architecture and Digital Design concepts; Very strong background in Verilog, System Verilog, and OOO coding techniques; Familiarity with scripting languages: perl/tcl/ruby/Bash/python; Strong analytical skills and attention to detail; Education Bachelor’s/Master’s degree in Computer Engineering, Computer Science, Electrical Engineering or similar.